The present invention relates to a termination circuit and an impedance matching device including the same, and more particularly, to technology for reducing an entire area of an impedance matching device.
Semiconductor devices may be implemented as integrated circuit (IC) chips such as central processing units (CPUs), memories, and gate arrays, and are incorporated into a variety of electrical products such as personal computers, servers and workstations. Semiconductor devices often include a receiving circuit configured to receive external signals via input pads, and an output circuit configured to provide internal signals to the outside via output pads.
As the operating speed of electrical products increases, a voltage-swing of a signal interfaced between semiconductor devices gradually reduces to minimize a delay time taken for signal transmission. However, in reducing the voltage-swing of the signal, effect of external noise significantly increases, causing severe signal reflectance at an interface terminal due to impedance mismatching. Such impedance mismatching is generally caused by external noise, variation of a power supply voltage, change in an operating temperature, change in a manufacturing process, and so on. The impedance mismatching may lead to a difficulty in high-speed transmission of data and distortion of output data. Therefore, if semiconductor devices receive the distorted output signal through an input/interface terminal, it frequently gives rise to problems such as a setup/hold failure, and an error in decision of an input level.
In particular, in order to resolve the above problems, a memory device requiring high-speed performance employs an impedance matching circuit, which is called an on die termination (ODT) device, near around an input pad inside an IC chip. In a typical ODT scheme, source termination is performed at a transmitting end by an output circuit, and parallel termination is performed by a termination circuit connected in parallel with respect to a receiving circuit coupled to the input pad.
ZQ calibration refers to a procedure of generating calibration codes which are varied with process, voltage and temperature (PVT) conditions. The resistance of the ODT device, e.g., a termination resistance at a DQ pad in a memory device, is calibrated using the calibration codes resulting from the ZQ calibration. The ZQ calibration is named because the calibration is performed using a ZQ node that is a node for calibration.
The following description will be made on a calibration circuit for generating impedance calibration codes, and a termination circuit for terminating input/output nodes by using the generated impedance calibration codes.
FIG. 1 is a circuit diagram of a conventional calibration circuit.
Referring to FIG. 1, the conventional calibration circuit includes a pull-up reference impedance unit 110, a dummy reference impedance unit 120, a pull-down reference impedance unit 130, a reference voltage generation unit 102, comparison units 103 and 104, and counting units 105 and 106.
Upon operation of the conventional calibration circuit, the comparison unit 103 compares a reference voltage VREF (generally,
            VDDQ      2        )    ,which is generated from the reference voltage generation unit 102, with a voltage of a calibration node ZQ, which is generated by a voltage division of an external resistor 101 connected to a calibration pad (hereinafter, referred to as 120Ω) and the pull-up reference impedance unit 110, and generates an up/down signal UP/DOWN.
The counting unit 105 receives the up/down signal UP/DOWN to generate pull-up impedance calibration codes PCODE<0:N>. The pull-up impedance calibration codes PCODE<0:N> adjusts the total impedance of the pull-up reference impedance unit 110 by turning on/off parallel resistors of the pull-up reference impedance unit 110 (the impedances of the parallel resistors are designed according to binary weights). The adjusted impedances of the pull-up reference impedance unit 110 again influence the voltage of the ZQ node and the above-described operations are repeated. As a result, the pull-up impedance calibration codes PCODE<0:N> are counted until the total impedance of the pull-up reference impedance unit 110 is equal to the impedance of the external resistor 101. The above-described operation is called a pull-up calibration operation.
The pull-up impedance calibration codes PCODE<0:N> generated by the pull-up calibration operation are inputted to the dummy reference impedance unit 120 to determine the total impedance of the dummy reference impedance unit 120. In the similar manner to the pull-up calibration operation, the pull-down calibration operation starts to calibrate a voltage of a node A to be equal to the reference voltage VREF by using the comparison unit 104 and the counting unit 106. That is, the total impedance of the pull-down reference impedance unit 130 is calibrated to be equal to the total impedance of the dummy reference impedance unit 120.
The impedance calibration codes PCODE<0:N> and NCODE<0:N> generated by the ZQ calibration operation are inputted to a termination circuit of FIG. 2 to adjust the termination impedance.
FIG. 2 is a circuit diagram of a conventional termination circuit.
The termination circuit refers to a circuit that receives the impedance calibration codes PCODE<0:N> and NCODE<0:N> from the calibration circuit of FIG. 1 to terminate interface pads.
The termination circuit includes pull-up termination impedance units 210, 220 and 230, and pull-down termination impedance units 240, 250 and 260. The termination circuit may include either of the pull-up termination impedance units 210, 220 and 230 and the pull-down termination impedance units 240, 250 and 260 according to a termination scheme.
The pull-up termination impedance units 210, 220 and 230 are designed to have the same configuration as the pull-up reference impedance unit 110 and to receive the pull-up impedance calibration codes PCODE<0:N> in the same manner. Therefore, the pull-up termination impedance units 210, 220 and 230 have the impedance of 120Ω just like the pull-up reference impedance unit 110. The pull-down termination impedance units 240, 250 and 260 are designed to have the same configuration as the pull-down reference impedance unit 130 and to receive the pull-down impedance calibration codes NCODE<0:N> in the same manner. Therefore, the pull-down termination impedance units 240, 250 and 260 have the impedance of 120Ω just like the pull-down reference impedance unit 130.
A pull-up termination enable signal PU_EN is a signal for enabling the pull-up termination operation, and a pull-down termination enable signal PD_EN is a signal for enabling the pull-down termination operation. When the pull-up termination enable signal PU_EN is disabled, the parallel resistors of the pull-up termination impedance units 210, 220 and 230 are turned-off. When the pull-down termination enable signal PD_EN is disabled, the parallel resistors of the pull-down termination impedance units 240, 250 and 260 are turned-off. “Off” conditions of the resistors means that the resistors are disconnected, that is, the termination operation is not performed.
Signals PU_60 and PU_40 are signals for setting the pull-up termination impedance. This is because the pull-up termination impedance is not always fixed, but is changed according to system environment. For example, semiconductor memory devices are designed to support termination impedances of 120Ω, 60Ω and 40Ω according to a mode register setting (MRS). The signal PU_60 is a signal for setting the pull-up termination impedance to 60Ω. When the signal PU_60 is enabled, the two pull-up termination impedance units 210 and 220 are enabled. Since the pull-up termination impedance units 210 and 220 each having the impedance of 120Ω are connected in parallel, the pull-up termination impedance becomes 60Ω. The signal PU_40 is a signal for setting the pull-up termination impedance to 40Ω. When the signal PU_40 is enabled, the three pull-up termination impedance units 210, 220 and 230 are enabled. Since the pull-up termination impedance units 210, 220 and 230 each having the impedance of 120Ω are connected in parallel, the pull-up termination impedance becomes 40Ω. When both the signals PU_60 and PU_40 are disabled, only the pull-up termination impedance unit 210 is enabled and thus the pull-up termination impedance becomes 120Ω.
Signals PD_60 and PD_40 are signals for setting the pull-down termination impedance. The signal PD_60 is a signal for setting the pull-down termination impedance to 60Ω. When the signal PD_60 is enabled, the two pull-down termination impedance units 240 and 250 are enabled. Since the pull-down termination impedance units 240 and 250 each having the impedance of 120Ω, are connected in parallel, the pull-down termination impedance becomes 60Ω. The signal PD_40 is a signal for setting the pull-down termination impedance to 40Ω. When the signal PD_40 is enabled, the three pull-down termination impedance units 240, 250 and 260 are enabled. Since the pull-down termination impedance units 240, 250 and 260 each having the impedance of 120Ω are connected in parallel, the pull-down termination impedance becomes 40Ω. When both the signals PD_60 and PD_40 are disabled, only the pull-down termination impedance unit 240 is enabled and thus the pull-down termination impedance becomes 120Ω.
The above-described termination circuit may be a main driver of an output driver. In case where the impedance of the output driver is set to 60Ω, if the signals PU_60 and PD_60 are enabled and the pull-up termination enable signal PU_EN is enabled, “high” data is outputted through an interface pad (in this case, a data output pad). If the pull-down termination enable signal PD_EN is enabled, “low” data is outputted through the interface pad.
As described above, the conventional termination circuit includes a plurality of termination impedance units to support various termination impedances, for example, 120Ω, 60Ω and 40Ω. In this case, the plurality of termination impedance units substantially increases the circuit area. Moreover, since the plurality of termination impedance units 210, 220, 230, 240, 250 and 260 are connected to the interface pad, a large capacitance component is generated in the interface pad, causing performance degradation of a chip.